In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). One technique for generating multiple clock signals having a phase spacing that is smaller than a delay element is to interpolate between the delay stage phases. Phase interpolators are typically controlled by an N bit interpolation control word that selects a desired one of 2N possible phases. It has been found that many phase interpolators exhibit non-linearity as the data rate of the incoming clock signal is varied.
In particular, it is known that improved linearity is achieved when the clock edges entering the phase interpolator have an edge rate, or slope, that is in a range approximately between the value of the delay between each clock edge and twice the value of the delay between each clock edge. A slope in this range ensures that the interpolator output does not change so quickly that it reaches a steady-state intermediate level before the arrival of the second clock edge, resulting in interpolator non-linearity. There is currently no effective mechanism, however, to maintain a desired slope as the data rate is varied.
A need therefore exists for improved techniques for interpolating two input clock signals to generate a clock signal having a phase between the phase of the two input clock signals. A further need exists for improved interpolation techniques that provide a highly linear phase interpolation transfer function.